1. Field of the Invention
This invention relates to integrated circuit assemblies, more particularly to a low-cost, slim, hermetically sealed integrated circuit package and method of manufacture without the normal lead frame, and avoiding plastic encapsulation or use of a ceramic housing.
2. Material Art
Various package schemes have been proposed and used in the integrated circuit (IC) chip art. These provide physical protection for the IC and external electrical connections to the integrated circuits of the chip. Very prevalent are designs including lead frames with extending lead fingers, with an IC mounted on a central part of the frame Interconnections, such as wire bonds, are made between pads on the IC and the fingers. The overall device, other than exteriorly extending leads, is then encapsulated with an epoxy or other plastic to form what is known, for example, as a DIP -- dual-in-line package or PLCC -- Plastic Leaded Chip Carrier. Other designs utilize a ceramic housing in which an IC is mounted and interconnect metallization provided on surfaces of the housing extending to an exterior position. Bonding wires are connected between IC pads and the metallization and a ceramic or metal lid is attached to the housing to complete the assembly. Ceramic packages are normally higher in cost than plastic packages and oft times must be custom-designed. Plastic packages with lead frames are susceptible to poor hermetic sealing due to penetration of moisture through the package to the chip by moisture traveling along plastic voids or by capillary action, resulting in degradation and reduced reliability. While plastic packages have been designed for insertion on printed circuit boards and the like using automatic insertion equipment, ceramic assemblies are generally more difficult to insert, though they are better than plastic assemblies in being hermetically sealed. Thermal expansion problems are present with respect to both plastic and ceramic chip carriers due to differences in the materials of the carrier and the semiconductor material used in the chip per se.
Other concerns of IC chip package designers and engineers are the costs of materials and manufacture including tooling and assembly, minimization of size, particularly the height of the assembly, short-runs and quick turn-around capability, density of IC input/output pins, low temperature processing and testability of the completed package.